1. Field of the Invention
This invention generally relates to integrated circuit (IC) memory fabrication and, more particularly, a high-density, high-speed crosspoint resistor memory array, applicable to ultra large-scale integrated (ULSI) memory chips and embedded memory applications, that uses a floating p-well.
2. Description of the Related Art
Electrically programmable resistance non-volatile memory devices have been demonstrated at room temperature conditions, although not in a functional array. High-density memories such as dynamic random access memory (DRAM) and Flash memory currently exist, having a small cell size, suggesting that the high-density integration of electrically programmable resistance non-volatile memory devices is also possible. However, DRAM fabrication is relatively complex. Flash memory is complex to operate, requiring high voltage programming. Further, there have been difficulties in scaling Flash memory down to a sub-micron cell size.
Conventionally, high-density crosspoint resistor RAM (R-RAM) memory has used an n+ silicon layer as either a bit line or word line. The R-RAM memory resistor is connected to the n+ layer through a p+ diffusion layer. The n+ bit (or word line) is fabricated onto the p-well. The junction capacitance between the n+ layer and the p-well is parasitic, providing a current leakage path for incoming signals. As a result, the high frequency operation of the array is degraded, or the bit (or the word) n+ line lengths must be kept relatively short.
FIG. 1 is a partial cross-sectional view of a trench isolated crosspoint R-RAM array (prior art). The top electrode (TE) is shown as word line, while the n+ layer is shown as a bit line. Alternately but not shown, the top electrode could a bit line and the n+ layer could be a word line. The contact to the n+ line, as shown, is the same metal that is used for the top electrode. Alternately, the contact can be any circuit interconnect metal. The n+ line is a distributed resistor/capacitor (RC) transmission line at high frequencies. The junction capacitance is the parasitic capacitance. A high-speed R-RAM operates with programming and the read pulse width of 10 nanoseconds, corresponding to a frequency of 100 megahertz (MHz). At this frequency, the parasitic capacitance at the n+ layer may significantly degrade the operating pulses, especially if the n+ layer bit line has a long length.
It would be advantageous if an R-RAM array could be fabricated with extremely small cell sizes, using relatively simple fabrication processes.
It would be advantageous if the capacitance of n+ layer bit or word lines in an R-RAM could be minimized, permitting the R-RAM to be fabricated with longer n+ layer line lengths, and operated at higher frequencies.
It would be advantageous if arrays with longer length n+ layer bit (word) lines could be fabricated, so that the number of cells in an R-RAM array could be increased.